Focused Ion Beam (FIB) techniques are increasingly being used in the semiconductor industry. On example of the use of such techniques is in circuit “editing” which allows designers to cut metal traces or add metal interconnections within an integrated circuit die. FIB circuit editing employs a finely focused gallium (Ga+) ion nanoscale resolution beam that has been used to image, etch, and deposit materials on an integrated circuit die with a high level of precision. The FIB process allows designers to cut and connect circuitry within the live device. The high-energy Ga+ ion beam can mill through conductors, and various types of gases can be used to either enhance milling precision or more effectively deposit conductive and dielectric materials. For instance, by utilizing the appropriate gas chemistries, material such as tungsten, platinum, and silicon dioxide can be precisely deposited.
To perform circuit edits, the FIB tool is coupled to a CAD navigation system that is used to locate an area of interest. The FIB circuit editing process employs design files to navigate to the area of interest, allowing subsurface features to be located and ensure that the right edits are made.
Typical FIB integrated circuit editing applications include debugging and optimizing devices in production, exploring and validating design changes, prototyping new devices without the need for mask set fabrication and fabrication runs, scaling fixes, and preventing or at least minimizing time-to-market delays.
In complex integrated circuit design, it is common to find functional bugs during post silicon stage. Logical function fixing typically requires at least a metal respin and in some cases a full base respin. Designers typically treat FIB as a best effort to avoid layout mask respin, and resort to layout mask respin for complicated bugs for which logic cell insertion is needed.
Post silicon stage editing via FIB has limited flexibility as it is destructive by nature. Common successful FIB editing is limited to simple reconnection, and is seldom successful for adding logical functions to repair or alter existing logic functions.
For post-silicon fixes, an approach of spare-gate sprinkling and/or gate-array filler cells are currently offered in the industry. These typically require alteration of the metal interconnect mask used to define the interconnect pattern of one or more metal layers to add new logic cell into silicon, i.e. a metal respin.